An integrated circuit (“IC”) is a device (e.g., a semiconductor device) or electronic system that includes many electronic components, such as transistors, resistors, diodes, etc. These components are often interconnected to form multiple circuit components, such as gates, cells, memory units, arithmetic units, controllers, decoders, etc. An IC includes multiple layers of wiring that interconnect the IC's electronic and circuit components.
Design engineers design ICs by transforming logical or circuit descriptions of the ICs' components into geometric descriptions, called design layouts. Design layouts typically include (1) circuit modules (i.e., geometric representations of electronic or circuit IC components) with pins and (2) interconnect lines (i.e., geometric representations of wiring) that connect the pins of the circuit modules. In this fashion, design layouts often describe the behavioral, architectural, functional, and structural attributes of the IC. To create design layouts, design engineers typically use electronic design automation (“EDA”) applications. These applications provide sets of computer-based tools for creating, editing, analyzing, and verifying design layouts. The applications also render the layouts on a display device or to storage for displaying later.
Fabrication foundries (“fabs”) manufacture ICs based on the design layouts using a photolithographic process. Photolithography is an optical printing and fabrication process by which patterns on a photolithographic mask (i.e., “photomask,” or “mask”) are imaged and defined onto a photosensitive layer coating a substrate. To fabricate an IC, photomasks are created using the IC design layout as a template. The photomasks contain the various geometries or shapes (i.e., features) of the IC design layout. The various geometries or shapes contained on the photomasks correspond to the various base physical IC elements that comprise functional circuit components such as transistors, interconnect wiring, vertical interconnect access (via) pads, as well as other elements that are not functional circuit elements but are used to facilitate, enhance, or track various manufacturing processes. Through sequential use of the various photomasks corresponding to a given IC in an IC fabrication process, a large number of material layers of various shapes and thicknesses with various conductive and insulating properties may be built up to form the overall IC and the circuits within the IC design layout.
As more circuit features are packed into an IC design layout (e.g., manufacturing processes at feature sizes of 14 nm and below), the resolution of the photolithographic process makes it extremely difficult to fabricate the geometries or shapes on a single lithography mask. The difficulty stems from constraining factors in traditional photolithographic processes that limit the effectiveness of current photolithographic processes. Some such constraining factors are the lights/optics used within the photolithographic processing systems. Specifically, the lights/optics are band limited due to physical limitations (e.g., wavelength and aperture) of the photolithographic process. Therefore, the photolithographic process cannot print beyond a certain minimum width of a feature, minimum spacing between features, and other such physical manufacturing constraints.
For a particular layer of the IC fabrication process, the pitch specifies the sum of the width of a feature and the space on one side of the feature separating that feature from a neighboring feature on the same layer. The minimum pitch for a layer is the sum of the minimum feature width and the minimum spacing between features on the same layer. Depending on the photolithographic process at issue, factors such as optics and wavelengths of light or radiation restrict how small the pitch may be made before features can no longer be reliably printed to a wafer or mask. As such, the smallest size of any features that can be created on a layer of an IC is limited by the minimum pitch for the layer.
FIG. 1 illustrates a typical pitch constraint of a photolithographic process. In FIG. 1, a pitch 110 acts to constrain the spacing between printable features 120 and 130 of a design layout. While other photolithographic process factors such as the threshold 140 can be used to narrow the width 150 of the features 120 and 130, such adjustments do not result in increased feature density without adjustments to the pitch 110. As a result, increasing feature densities beyond a certain threshold is infeasible via a pitch constrained single exposure process.
To enhance the feature density, the shapes on a single layer can be manufactured on two different photolithographic masks. This approach is often referred to as “Double Patterning Lithography (DPL)” technology. FIG. 2 illustrates an example of this approach. In FIG. 2, a design layout 205 specifies three features 210-230 that are pitch constrained and therefore cannot be photolithographically printed with a conventional single exposure process. Analysis of the characteristics (e.g., the band limitation) of the available photolithographic process and of the design layout 205 results in the decomposition of the design layout 205 into a first exposure 240 for printing features 210 and 230 and a second exposure 250 for printing feature 220. As such, the features 210 and 230 are assigned to a first photomask for printing during the first exposure 240 and feature 220 is assigned to a second photomask for printing during the second exposure 250.
FIG. 3 illustrates sending five shapes 301-305 of a design layout 300 to two different masks. The shape pairs of the shapes 301 and 302; the shapes 302 and 303; the shapes 303 and 304; and the shapes 304 and 305 are all pitch constrained. Therefore, the two shapes of each pair must be sent to two different masks 310 and 315. Accordingly, the shapes 301 and 303 are sent to a first mask 310. That is, the shapes 301 and 303 are printed during a first exposure in order to produce contours 320. Similarly, the shapes 302, 304, and 305 are sent to a second mask 315. That is, the shapes 302, 304, and 305 are printed during a second exposure in order to produce contours 325. The resulting union of the contours 320 and 325 generates pattern 330 that is sufficient to approximately reproduce the original design layout 300.
To use DPL technology, the layout designers need to follow a set of design rules or constraints while designing the layout such that the shapes on a single design layer can be successfully fabricated using two different masks. However, even when the design rules are met, other issues may arise which affect the DPL process. The denser the layout of features on a screen is, even when it meets the necessary design rules, the higher the likelihood for potential problems with the printing process.